Chip giants start war on 2nm

In January this year, the first High-NA EUV lithography machine produced by ASML in the Netherlands was unveiled for the first time. This behemoth, with a total weight of about 150 tons and requiring 250 containers to fit, can further shrink the world’s most advanced chip manufacturing process from 3 nanometers to 2 nanometers. Its emergence also marked the first shot for semiconductor manufacturers to mass-produce 2-nanometer chips.

As the world’s number one wafer foundry, TSMC is the fastest player.

According to Taiwan’s “Business Times” report on March 29, TSMC’s 2-nanometer process layout has been accelerated across the board. The company’s Fab20 P1 plant in Baoshan, Hsinchu will carry out equipment installation projects in April to prepare for the mass production of its 2-nanometer chips. It is expected that TSMC Baoshan P1 The three advanced process wafer fabs, P2 and Kaohsiung, will all enter mass production in 2025, attracting customers such as Apple, Nvidia, AMD and Qualcomm to compete for production capacity.

Although TSMC responded to the media saying that it would not comment, according to the roadmap announced by the company at an investor meeting in July 2022, the 2-nanometer process will be trial-produced in 2024 and mass-produced in 2025. TSMC is on track to start production of 2-nanometer chips this year as scheduled.

In addition to TSMC, Samsung and Intel are also catching up on the 2-nanometer track.

As an old rival that has been fighting with TSMC in 5nm and 3nm for many years, Samsung is also closing in on the 2nm competition. According to Korean media ZDNet, Samsung has informed customers and partners that it will rename its second-generation 3nm process to 2nm starting from the beginning of this year. Although the company has never responded to the outside world’s doubts about its “leading its competitors by changing its name”, it has officially announced that 2nm may start mass production before the end of this year.

Intel is the “new opponent” returning to the game. In the early years, Intel started its business by manufacturing chips, but later it was left behind by TSMC and Samsung. After successive failures in the 10-nanometer and 7-nanometer processes, Intel was obviously lagging behind in the field of chip manufacturing. Almost all advanced process chips were outsourced to TSMC.

But since current CEO Pat Gelsinger came to power, the company has planned to revive the foundry business of manufacturing chips under his leadership. At the first Intel Foundry Direct Connect conference held in February, Intel announced its intel 18A (according to Intel’s official definition as 1.8 nanometers, but the industry usually compares it horizontally with its opponents’ 2 nanometers) and more advanced future process routes. Figure, and the planned mass production time of Intel 18A is similar to that of the two major competitors. It will be ready for mass production in the second half of 2024, and products based on 18A will be launched in 2025.

Just one year after TSMC and Samsung launched 3-nanometer process chips in 2022, the 2-nanometer competition has already been put on the agenda. Faced with TSMC’s leading position as the world’s largest chip foundry, both Samsung and Intel regard 2 nanometers as an opportunity to overtake in a corner – the former has vowed to regain the top spot in the chip market within three years, and the latter has vowed The world’s second largest foundry will be built by 2030.

2nm becomes a new battlefield
According to the classic Moore’s Law in the semiconductor industry, the number of transistors that an integrated circuit can accommodate will double every 18 months, and the performance will also double accordingly. The well-known several nanometers usually refers to the size of the transistor. In order to accommodate as many transistors as possible on the integrated circuit, from 10 nanometers to 7 nanometers, then to 5 nanometers and 3 nanometers, the size of the transistors is getting smaller and smaller, and the chip is also smaller. The response is getting smaller and smaller.

2nm will first appear in 2021. IBM released the world’s first 2-nanometer chip at that time. According to official information, IBM’s 2nm process chip puts about 50 billion transistors on a chip the size of a fingernail. Compared with the 7nm process chip, its computing speed will be 45% faster and its efficiency will be improved. 75%. However, it is generally believed in the industry that IBM, as a research institution, does not yet have the ability to mass-produce, and it will take some time for 2-nanometer process chips to move from the laboratory to mass production.

As the size of chip manufacturing processes continues to shrink, chip manufacturers need to solve more problems, such as current leakage. In TSMC’s technical solution for 2-nanometer chips, the GAAFET architecture was used for the first time. The GAAFET architecture stands for Fully Surrounded Gate Field Effect Transistor. Unlike the FinFET architecture used below the 14nm process, GAAFET uses gate electrodes to cover four sides of the current channel instead of the traditional three, allowing the transistor to continue to shrink without leakage. , allowing significant performance improvements at reduced operating power.

Similar landmark solutions include wafer backside power supply. Compared with traditional front-side power supply, this technology can reduce voltage drop, thereby reducing power consumption and significantly improving chip performance.

Previously, Samsung has adopted the above two technical solutions in its 3nm process, and Intel is also continuing to follow up. Many industry insiders said that starting from 2 nanometers, GAAFET and back power supply will become the industry standard.

Fang Liang, investment director of Quandexue, who has long been concerned about semiconductor manufacturing processes, told Jiemian News that each generation of manufacturing processes is roughly divided into two stages: research and development and mass production. The chip factory first invests in manufacturing a small number of wafers in the laboratory at all costs, and then masters the technology and improves the yield rate to 30%-40%; then the mass production department will take over and carry out risk trial production and small-scale mass production in sequence. , and then to large-scale mass production, continuously pushing up the yield rate and increasing production capacity. When the chip yield reaches about 60%-70%, it can basically guarantee that “it will be enough for the commercialization stage.”

When a chip manufacturer can maintain a yield rate of more than 80% on a certain generation of process chips and its monthly production capacity climbs to 100,000 pieces, it can basically gain a firm foothold in this generation of advanced process technology.

At the same time, in order to maintain a fast enough iteration rhythm, chip manufacturers will maintain the workflow of “mass production, research and development, and reserve generation”.

According to previous reports by Finance Eleven, TSMC generally has three teams that simultaneously carry out research on the third-generation process. One team is engaged in the research and development and yield improvement of the 3-nanometer process, another team is engaged in the research and development of the 2-nanometer process, and another team will conduct research and development of the 1.5-nanometer process path. After the 3nm process is mass-produced, the 3nm process team will jump to the 1.5nm team to join the research and development, and the 1.5nm team will jump to the next generation smaller process path to research and development, and so on. Therefore, it seems to the outside world that the cycle of launching a new generation of advanced processes every two years, but the internal layout often takes five or six years.

According to the timetables announced by Samsung, TSMC and Intel, 2nm will achieve mass production in 2025, and that year is regarded as a watershed by the industry. As the chip size becomes smaller and smaller, the cost of each generation of process is greater, and the performance improvement is smaller.

The late Gordon Moore, the proposer of Moore’s Law and the late Intel founder, once predicted that the limit of Moore’s Law would arrive around 2025. TSMC founder Zhang Zhongmou also held the same view.

The battle for giant positions
Qiao An, an analyst at TrendForce, said in an interview that judging from the current customer status of each 2nm chip, TSMC is the most active, with more than 10 customers introducing R&D; Samsung’s 2nm foundation is still based on its 3nm chip In terms of nano-process technology, it is necessary to continue to observe the improvement of yield; Intel’s independent services to external customers are mainly focused on the Intel 18A process. She judged that it is not expected to see 2-nanometer products appear on the market until 2026.

The iteration of chip manufacturing processes has formed a mature ecosystem involving multiple industry players, technologies and market dynamics, including not only semiconductor manufacturers such as TSMC and Samsung, but also design and IP companies such as NVIDIA and AMD, such as Apple and MediaTek , Qualcomm smart terminal customers often need to participate in joint development.

He Hui, director of semiconductor research at Omdia, an international research institution focusing on the technology industry, told reporters that mature chip manufacturers such as TSMC have always maintained a relatively fixed iteration model. Once a certain generation of process chips is mass-produced, it will be released to the outside world in the same year. Announce the goals for the next generation, including process technology and mass production time.

He Hui judged that a yield rate of 80% is the basic standard for TSMC’s large-scale mass production. For its internal mature technology processes, such as 5 nanometers, the yield rate should have exceeded 95%, and large-scale mass production can already be profitable.

As the world’s number one chip manufacturer, TSMC is the dominant player in this field in terms of technological maturity, production capacity and scale. The semiconductor industry has long been a market structure with extremely obvious head effects. “The boss eats meat, the second brother drinks soup, and the third child goes hungry” is the norm.

On the track of impacting 2nm, TSMC has also been several positions ahead of its competitors. The latest generation of 3nm process is the most typical one. TSMC is currently generally considered to be the only winner in the market.

Previously, the main opponent in the fierce competition with TSMC for 3 nanometers was Samsung. In June 2022, Samsung announced the launch of its 3-nanometer process technology, which was nearly 6 months ahead of TSMC. However, it was subsequently exposed by the media that it fell into a yield black hole and was unable to meet customer requirements.

Industry insiders analyzed to reporters that although Samsung is firmly committed to TSMC on 7 nanometers, 5 nanometers and 3 nanometers, from the perspective of customer choice, it is mainly as a “secondary supplier” to TSMC. According to a TrendFoce research report, Qualcomm will choose TSMC and Samsung as the “dual suppliers” of the latest generation Snapdragon processor 3nm chips, but eventually gave up due to yield issues and switched to TSMC. Currently, there are no reports of major customers paying for Samsung’s 3-nanometer chips in the industry.

In stark contrast, since TSMC launched the 3-nanometer process in December 2022, its yield rate and production capacity have steadily climbed, and it has successively won orders from major customers such as Apple, Qualcomm, and MediaTek. The output of 3-nanometer chips is beginning to gradually increase, with the goal of Achieve 80% capacity utilization in the second half of 2024.

Currently, smartphone manufacturers represented by Apple on the market are the main customers using the 3-nanometer process, and Android phone manufacturers will release corresponding products one after another.

2025 is the year when the 3-nanometer process will be popularized, and smartphone CPU SoC chips (system-on-chip) will be the most important application. According to Taiwanese media Wccftech, TSMC has planned to increase its 3-nanometer monthly production capacity to 100,000 pieces in 2024, while focusing on further improving the yield rate. At the same time, Samsung is also doing its best to improve yield and win over users.

Among the three, Intel has lacked a presence in the chip manufacturing field for many years.

According to TrendForce’s statistics of the world’s top ten wafer foundries over the years, TSMC ranks first with a market share of around 60%, Samsung ranks second with about 10%, and Intel was only selected for the first time in the third quarter of 2023, with a share of only 1 %, and was surpassed by other manufacturers in the next quarter.

However, some industry insiders told reporters that Intel began internal reorganization in the first quarter of this year to completely separate design and manufacturing. Making the wafer foundry business independent and responsible for its own profits and losses is an important reform. It is also worth noting that Intel is the first customer in the industry to receive the first batch of 6 units of the High-NA EUV lithography machines produced by ASML this year. This series of actions can be interpreted as the veteran chip giant’s “strong man breaks his wrist” and Determination to develop 2 nanometers.

The current market demand for advanced process chips is only increasing. With the outbreak of the AI craze, NVIDIA data center GPU chips have become a global rush. Although compared to smartphone SoC chips, data center chips have a more conservative demand for advanced processes. The most advanced B200 chip released at the NVIDIA GTC conference still uses It is TSMC’s 4-nanometer solution, but with the rapid expansion of computing power demand, it will soon push the total number of advanced process chips to an unprecedented level. The production capacity of advanced process chips is still the target of competition among various companies.

TSMC Chairman Liu Deyin recently published a signed article on the IEEE website, comparing the semiconductor industry’s efforts to reduce chip size over the past 50 years to “walking in a tunnel.” Now we are getting closer and closer to the limit of Moore’s Law. The industry has reached the end of the tunnel. Semiconductor technology will become more difficult to develop. 2 nanometers will be a key battle for chip giants to seize the market.