Intel CEO Pat Gelsinger did not shy away from the losses faced by the business and said that 2024 will be the most serious year of operating losses for the company’s chip manufacturing business.

At the same time, he also gave a prediction that the business will achieve operating breakeven by the end of 2030. At that time, the company’s goal is to achieve a gross profit margin of 40% and an operating profit margin of 30% under non-GAAP.

After the above news was released, Intel’s closing price that day was $43.94 per share, down 4.1% after the market closed.

As an old American semiconductor giant, Intel has not adopted the “Fabless” model popular in the industry, that is, it is only responsible for chip design and outsources manufacturing to foundries such as TSMC. Instead, it has always integrated design and manufacturing. The “Integrated Device Manufacturer” (IDM) model.

At an online analyst meeting in June last year, the company disclosed for the first time that it would split its design and manufacturing business in the first quarter of 2024. The foundry division will be completely independent and responsible for its own profits and losses.

In February this year, at the IFS Direct Connect 2024 conference in California, Intel announced that it would officially change the name of its wafer business Intel Foundry Services to Intel Foundry. The company also publicly demonstrated the mass production progress of its 1.8nm chip process intel18A, as well as its process roadmap for the next ten years including the more advanced Intel 14A (corresponding to 1.4nm) process.

According to SEC filings, Intel’s business is divided into two parts based on “OEM-Product”. The product divisions include Client Computing Group (CCG), Data Center and Artificial Intelligence Group (DCAI), and Network and Edge Group (NEX). ). Foundry consists of foundry technology research and development, foundry manufacturing and supply chain, and foundry services. It has now become an independent operating department (i.e. Intel Foundary) with its own profit and loss statement.

According to the split plan, the independent foundry department will calculate revenue from external customers and Intel products based on market pricing, as well as R&D and manufacturing costs that have been allocated to the company’s product departments in the past. According to this arrangement, the profits of Intel’s product department will also increase significantly. The company plans to achieve a gross profit margin of 60% and an operating profit margin of 40% under non-standard accounting standards by the end of 2030.

In addition, Intel’s management has previously set goals for its post-independence wafer foundry business. It will challenge its main competitors, namely TSMC and Samsung, in the field of chip manufacturing, vowing to become the world’s second largest foundry by 2030. .

In order to support this ambitious plan, Intel has fully opened up to accept wafer foundry orders from external customers. “We are willing to OEM chips for any company, including our competitor AMD.” Kissinger had previously publicly called on customers to request orders. At the conference in February, both Microsoft and ARM signed on-site cooperation agreements with Intel. The company estimated that wafer foundry orders will reach US$15 billion, higher than the original expectation of US$10 billion.

The latest statistics from the international consulting agency CounterPoint show that TSMC ranks first with a market share of 61%, Samsung ranks second with a market share of 14%, and Intel is shortlisted in the top ten, but the market Accounting for less than 1%, there is still a big gap with its opponents.

Two senior industry insiders who study semiconductor manufacturing processes told Jiemian News that Intel had previously lacked a presence in the chip manufacturing field for a long time, but in recent years its independent foundry business has snapped up ASML’s most advanced EUV lithography machines and promoted ” A series of measures such as the “Five Nodes in Four Years” chip advanced manufacturing process still show the determination of this old chip giant to revitalize chip manufacturing.

In addition, as one of the few chip companies in the United States with manufacturing capabilities, Intel’s industrial policy support from the government is also an advantage that cannot be ignored.

Last month, the company received $8.5 billion in direct funding subsidies from the U.S. Chips and Science Act, which may be the largest payment of its kind currently issued by the Chip Act. The company is also eligible for $11 billion in future federal loans to advance construction of its factories in Arizona, New Mexico, Ohio and Oregon.

In addition, Intel was also selected into the first batch of the EU’s 43 billion euro subsidy plan for the European version of the “Chip Act”. Its new factory in Germany with a total investment of 30 billion euros is the first project to be implemented under this bill.

According to the analysis of the above-mentioned industry insiders, the chip foundry market has long been concentrated on leading manufacturers, and TSMC has almost monopolized the manufacturing of advanced process chips. However, as the United States and the European Union have successively introduced policies to subsidize the semiconductor industry, major countries have increasingly called for the chip manufacturing supply chain to return to their home countries, which may reshape the competitive landscape of the global market.

Against this background, whether Intel can take advantage of the situation and gain a place deserves long-term attention.

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As the world’s number one wafer foundry, TSMC is the fastest player.

According to Taiwan’s “Business Times” report on March 29, TSMC’s 2-nanometer process layout has been accelerated across the board. The company’s Fab20 P1 plant in Baoshan, Hsinchu will carry out equipment installation projects in April to prepare for the mass production of its 2-nanometer chips. It is expected that TSMC Baoshan P1 The three advanced process wafer fabs, P2 and Kaohsiung, will all enter mass production in 2025, attracting customers such as Apple, Nvidia, AMD and Qualcomm to compete for production capacity.

Although TSMC responded to the media saying that it would not comment, according to the roadmap announced by the company at an investor meeting in July 2022, the 2-nanometer process will be trial-produced in 2024 and mass-produced in 2025. TSMC is on track to start production of 2-nanometer chips this year as scheduled.

In addition to TSMC, Samsung and Intel are also catching up on the 2-nanometer track.

As an old rival that has been fighting with TSMC in 5nm and 3nm for many years, Samsung is also closing in on the 2nm competition. According to Korean media ZDNet, Samsung has informed customers and partners that it will rename its second-generation 3nm process to 2nm starting from the beginning of this year. Although the company has never responded to the outside world’s doubts about its “leading its competitors by changing its name”, it has officially announced that 2nm may start mass production before the end of this year.

Intel is the “new opponent” returning to the game. In the early years, Intel started its business by manufacturing chips, but later it was left behind by TSMC and Samsung. After successive failures in the 10-nanometer and 7-nanometer processes, Intel was obviously lagging behind in the field of chip manufacturing. Almost all advanced process chips were outsourced to TSMC.

But since current CEO Pat Gelsinger came to power, the company has planned to revive the foundry business of manufacturing chips under his leadership. At the first Intel Foundry Direct Connect conference held in February, Intel announced its intel 18A (according to Intel’s official definition as 1.8 nanometers, but the industry usually compares it horizontally with its opponents’ 2 nanometers) and more advanced future process routes. Figure, and the planned mass production time of Intel 18A is similar to that of the two major competitors. It will be ready for mass production in the second half of 2024, and products based on 18A will be launched in 2025.

Just one year after TSMC and Samsung launched 3-nanometer process chips in 2022, the 2-nanometer competition has already been put on the agenda. Faced with TSMC’s leading position as the world’s largest chip foundry, both Samsung and Intel regard 2 nanometers as an opportunity to overtake in a corner – the former has vowed to regain the top spot in the chip market within three years, and the latter has vowed The world’s second largest foundry will be built by 2030.

2nm becomes a new battlefield
According to the classic Moore’s Law in the semiconductor industry, the number of transistors that an integrated circuit can accommodate will double every 18 months, and the performance will also double accordingly. The well-known several nanometers usually refers to the size of the transistor. In order to accommodate as many transistors as possible on the integrated circuit, from 10 nanometers to 7 nanometers, then to 5 nanometers and 3 nanometers, the size of the transistors is getting smaller and smaller, and the chip is also smaller. The response is getting smaller and smaller.

2nm will first appear in 2021. IBM released the world’s first 2-nanometer chip at that time. According to official information, IBM’s 2nm process chip puts about 50 billion transistors on a chip the size of a fingernail. Compared with the 7nm process chip, its computing speed will be 45% faster and its efficiency will be improved. 75%. However, it is generally believed in the industry that IBM, as a research institution, does not yet have the ability to mass-produce, and it will take some time for 2-nanometer process chips to move from the laboratory to mass production.

As the size of chip manufacturing processes continues to shrink, chip manufacturers need to solve more problems, such as current leakage. In TSMC’s technical solution for 2-nanometer chips, the GAAFET architecture was used for the first time. The GAAFET architecture stands for Fully Surrounded Gate Field Effect Transistor. Unlike the FinFET architecture used below the 14nm process, GAAFET uses gate electrodes to cover four sides of the current channel instead of the traditional three, allowing the transistor to continue to shrink without leakage. , allowing significant performance improvements at reduced operating power.

Similar landmark solutions include wafer backside power supply. Compared with traditional front-side power supply, this technology can reduce voltage drop, thereby reducing power consumption and significantly improving chip performance.

Previously, Samsung has adopted the above two technical solutions in its 3nm process, and Intel is also continuing to follow up. Many industry insiders said that starting from 2 nanometers, GAAFET and back power supply will become the industry standard.

Fang Liang, investment director of Quandexue, who has long been concerned about semiconductor manufacturing processes, told Jiemian News that each generation of manufacturing processes is roughly divided into two stages: research and development and mass production. The chip factory first invests in manufacturing a small number of wafers in the laboratory at all costs, and then masters the technology and improves the yield rate to 30%-40%; then the mass production department will take over and carry out risk trial production and small-scale mass production in sequence. , and then to large-scale mass production, continuously pushing up the yield rate and increasing production capacity. When the chip yield reaches about 60%-70%, it can basically guarantee that “it will be enough for the commercialization stage.”

When a chip manufacturer can maintain a yield rate of more than 80% on a certain generation of process chips and its monthly production capacity climbs to 100,000 pieces, it can basically gain a firm foothold in this generation of advanced process technology.

At the same time, in order to maintain a fast enough iteration rhythm, chip manufacturers will maintain the workflow of “mass production, research and development, and reserve generation”.

According to previous reports by Finance Eleven, TSMC generally has three teams that simultaneously carry out research on the third-generation process. One team is engaged in the research and development and yield improvement of the 3-nanometer process, another team is engaged in the research and development of the 2-nanometer process, and another team will conduct research and development of the 1.5-nanometer process path. After the 3nm process is mass-produced, the 3nm process team will jump to the 1.5nm team to join the research and development, and the 1.5nm team will jump to the next generation smaller process path to research and development, and so on. Therefore, it seems to the outside world that the cycle of launching a new generation of advanced processes every two years, but the internal layout often takes five or six years.

According to the timetables announced by Samsung, TSMC and Intel, 2nm will achieve mass production in 2025, and that year is regarded as a watershed by the industry. As the chip size becomes smaller and smaller, the cost of each generation of process is greater, and the performance improvement is smaller.

The late Gordon Moore, the proposer of Moore’s Law and the late Intel founder, once predicted that the limit of Moore’s Law would arrive around 2025. TSMC founder Zhang Zhongmou also held the same view.

The battle for giant positions
Qiao An, an analyst at TrendForce, said in an interview that judging from the current customer status of each 2nm chip, TSMC is the most active, with more than 10 customers introducing R&D; Samsung’s 2nm foundation is still based on its 3nm chip In terms of nano-process technology, it is necessary to continue to observe the improvement of yield; Intel’s independent services to external customers are mainly focused on the Intel 18A process. She judged that it is not expected to see 2-nanometer products appear on the market until 2026.

The iteration of chip manufacturing processes has formed a mature ecosystem involving multiple industry players, technologies and market dynamics, including not only semiconductor manufacturers such as TSMC and Samsung, but also design and IP companies such as NVIDIA and AMD, such as Apple and MediaTek , Qualcomm smart terminal customers often need to participate in joint development.

He Hui, director of semiconductor research at Omdia, an international research institution focusing on the technology industry, told reporters that mature chip manufacturers such as TSMC have always maintained a relatively fixed iteration model. Once a certain generation of process chips is mass-produced, it will be released to the outside world in the same year. Announce the goals for the next generation, including process technology and mass production time.

He Hui judged that a yield rate of 80% is the basic standard for TSMC’s large-scale mass production. For its internal mature technology processes, such as 5 nanometers, the yield rate should have exceeded 95%, and large-scale mass production can already be profitable.

As the world’s number one chip manufacturer, TSMC is the dominant player in this field in terms of technological maturity, production capacity and scale. The semiconductor industry has long been a market structure with extremely obvious head effects. “The boss eats meat, the second brother drinks soup, and the third child goes hungry” is the norm.

On the track of impacting 2nm, TSMC has also been several positions ahead of its competitors. The latest generation of 3nm process is the most typical one. TSMC is currently generally considered to be the only winner in the market.

Previously, the main opponent in the fierce competition with TSMC for 3 nanometers was Samsung. In June 2022, Samsung announced the launch of its 3-nanometer process technology, which was nearly 6 months ahead of TSMC. However, it was subsequently exposed by the media that it fell into a yield black hole and was unable to meet customer requirements.

Industry insiders analyzed to reporters that although Samsung is firmly committed to TSMC on 7 nanometers, 5 nanometers and 3 nanometers, from the perspective of customer choice, it is mainly as a “secondary supplier” to TSMC. According to a TrendFoce research report, Qualcomm will choose TSMC and Samsung as the “dual suppliers” of the latest generation Snapdragon processor 3nm chips, but eventually gave up due to yield issues and switched to TSMC. Currently, there are no reports of major customers paying for Samsung’s 3-nanometer chips in the industry.

In stark contrast, since TSMC launched the 3-nanometer process in December 2022, its yield rate and production capacity have steadily climbed, and it has successively won orders from major customers such as Apple, Qualcomm, and MediaTek. The output of 3-nanometer chips is beginning to gradually increase, with the goal of Achieve 80% capacity utilization in the second half of 2024.

Currently, smartphone manufacturers represented by Apple on the market are the main customers using the 3-nanometer process, and Android phone manufacturers will release corresponding products one after another.

2025 is the year when the 3-nanometer process will be popularized, and smartphone CPU SoC chips (system-on-chip) will be the most important application. According to Taiwanese media Wccftech, TSMC has planned to increase its 3-nanometer monthly production capacity to 100,000 pieces in 2024, while focusing on further improving the yield rate. At the same time, Samsung is also doing its best to improve yield and win over users.

Among the three, Intel has lacked a presence in the chip manufacturing field for many years.

According to TrendForce’s statistics of the world’s top ten wafer foundries over the years, TSMC ranks first with a market share of around 60%, Samsung ranks second with about 10%, and Intel was only selected for the first time in the third quarter of 2023, with a share of only 1 %, and was surpassed by other manufacturers in the next quarter.

However, some industry insiders told reporters that Intel began internal reorganization in the first quarter of this year to completely separate design and manufacturing. Making the wafer foundry business independent and responsible for its own profits and losses is an important reform. It is also worth noting that Intel is the first customer in the industry to receive the first batch of 6 units of the High-NA EUV lithography machines produced by ASML this year. This series of actions can be interpreted as the veteran chip giant’s “strong man breaks his wrist” and Determination to develop 2 nanometers.

The current market demand for advanced process chips is only increasing. With the outbreak of the AI craze, NVIDIA data center GPU chips have become a global rush. Although compared to smartphone SoC chips, data center chips have a more conservative demand for advanced processes. The most advanced B200 chip released at the NVIDIA GTC conference still uses It is TSMC’s 4-nanometer solution, but with the rapid expansion of computing power demand, it will soon push the total number of advanced process chips to an unprecedented level. The production capacity of advanced process chips is still the target of competition among various companies.

TSMC Chairman Liu Deyin recently published a signed article on the IEEE website, comparing the semiconductor industry’s efforts to reduce chip size over the past 50 years to “walking in a tunnel.” Now we are getting closer and closer to the limit of Moore’s Law. The industry has reached the end of the tunnel. Semiconductor technology will become more difficult to develop. 2 nanometers will be a key battle for chip giants to seize the market.

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In the great transformation of the world pattern, peace has become a fairy tale. It is unpredictable whether the prices of PCB, MCU, and CPU electronic components will rise or fall in 2025

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Wishing you a Merry Christmas filled with laughter, wonder, and delightful moments. May this festive season bring you a well-deserved break and a chance to rejuvenate. Thank you for your trust and partnership. Merry Christmas!

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Realize the industrialization of core key products
In recent years, the application proportion of third-generation semiconductors represented by silicon carbide (SiC) and gallium nitride (GaN) in consumer electronics, energy power, new energy vehicles and other fields has gradually increased, demonstrating unique advantages different from silicon based materials. Semiconductor new materials are reshaping the new competitive landscape of the global semiconductor industry.
Yang Fuhua, vice chairman and secretary-general of the third generation semiconductor industry technology innovation strategic alliance, and former deputy director of the Institute of Semiconductor Research of the Chinese Academy of Sciences, when introducing the development status and trend of the third generation semiconductor industry, said that China’s third generation semiconductor industry has entered a growth period, with steady technology improvement, continuous capacity release, gradual improvement of the ecosystem, continuous enhancement of independent and controllable capabilities, rapid development of enterprises, and expansion of product shipping channels, New progress has been made in strengthening the supply chain, application side cooperation, and market promotion, and the overall competitive strength is constantly improving.
According to CASA Research, the domestic market size of silicon carbide and gallium nitride power electronic devices in 2022 is about 10.55 billion yuan, a year-on-year increase of 48.4%. Based on data from different sources, it is predicted that the overall penetration rate of silicon carbide and gallium nitride power devices in China will be between 6% and 8% in 2022. “Yang Fuhua predicts that the market size of silicon carbide and gallium nitride power devices in 2026 will reach 36.6 billion yuan, and the CAGR (annual compound growth rate) may reach 36.5%.
Compared to the considerable growth expectations, the production capacity of silicon carbide is lower than expected. Currently, the international market has been in short supply of silicon carbide for a long time, and orders continue to be full.
Yang Fuhua said that although with the continuous investment of silicon carbide and gallium nitride resources, the continuous improvement of technology, the stability of products and the continuous decline of prices, on the other hand, silicon carbide and gallium nitride are mainly accepted in emerging markets such as electric vehicles, new energy, fast charging consumer power supply, and it still takes a long time to compete with Si products in traditional fields.
At a time when the third generation semiconductor (wide bandgap semiconductor) is in the ascendant, the fourth generation semiconductor (ultra wide bandgap semiconductor) material has also gradually launched a market game.
Referring to the current research, development and application of ultra wide band gap, equipment and auxiliary materials at home and abroad, Yang Fuhua said that the research heat of gallium oxide abroad is high, equipment and devices are developing rapidly, and many research achievements on gallium oxide are basically from Japan. On the other hand, although there are many universities and research institutes conducting research in China, there are relatively few entrepreneurial enterprises. In terms of equipment and auxiliary materials, foreign manufacturers are currently at least one generation ahead of domestic manufacturers in terms of equipment product update pace, and their product structure is rich, and prices are also being adjusted accordingly.
Yang Fuhua believes that an industrial system and ecosystem for collaborative innovation should be established, and puts forward four suggestions in this regard:

Firstly, establish a clear and systematic task oriented industry university research innovation consortium, accelerate iterative research and development, connect the industrial chain, achieve the industrialization of core key products, and promote the overall industry to reach international advanced levels.
Secondly, build an open and high-level professional national level platform, and strengthen the construction of national systematic capabilities in basic materials, design, technology, equipment, testing, standards, and other aspects.
Thirdly, strengthen precise international and regional cooperation, promote project cooperation and platform construction under the framework of intergovernmental cooperation, and carry out regular personnel exchange and technical cooperation.
Fourthly, explore the construction of a technology finance network chain, promote social capital through downstream feedback and upstream methods, and explore new cooperation models of platforms+incubators+funds+bases, as well as the integration and development of large and small enterprises.
Need to strengthen collaborative innovation between industry, academia, and research, and accelerate product technology iteration
In the fierce international competition, how can China’s semiconductor industry accelerate updates and breakthroughs? How to forge long and compensate short, maintain and stabilize the chain? What are the needs and difficulties for enterprises in the process of marketization, specialization, and internationalization of the domestic semiconductor industry?
In response, multiple experts from the business community shared their observations. The head of a power semiconductor device manufacturer stated that power semiconductor devices are currently in the ascendant in the field of new energy. However, in the application process of third-generation semiconductor materials, domestic technology reserves are still insufficient. “Foreign countries have already developed to the 7th and 8th generations, and we are still around the 4th generation
The head of a company engaged in the development of etching and ion implantation machines stated that due to the rise of international trade protectionism, the company has been affected to some extent during international technology introduction and mergers and acquisitions. In addition, in order to meet the constantly changing market demand, there are also many new challenges in new processes, materials, and processes, which require quick adaptation to difficulties and pain points.
The head of an enterprise engaged in the production of integrated circuit components stated that the current industry chain in the field of semiconductor integrated circuits in China is not yet perfect, especially for some components, upstream raw materials, and electronic components, which have weak domestic supporting capabilities. Even some special stainless steel products do not have particularly mature solutions in China.
Regarding the pain points and difficulties faced by the current industry, Meng Xiangjiu, Secretary General of the Shandong Semiconductor Industry Association, stated that China’s semiconductor industry has a relatively small share of the high-end market, which is both a challenge and an opportunity. While overcoming difficulties, it will also usher in a huge market.
From the perspective of industry associations, Meng Xiangjiu shared several suggestions. He stated that collaboration between industry, academia, and research in the semiconductor industry requires collaborative innovation, which involves joint research and development among research institutions, enterprises, and users; To fully utilize public technology service platforms and various new research and development institutions, accelerate product technology iteration, and enable products to better cater to the market; Localized products also need to obtain industrialization certification; For production enterprises that affect their production capacity due to the use of domestic substitute products, the state should also provide appropriate support policies.

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They are the ST VIPer series introduction, the advantages of integrated GAN chips, VIPerGaN performance introduction, and key test results of the solution. Next, let’s enter the first part of this speech, ST VIPer’s series introduction.
The above is the product line of the VIPerPlus series, developed by Italian Semiconductor for the power supply field. The VIPerPlus series products have undergone more than 20 years of iterative updates, combined with long-term product running-in and debugging with customers, achieving higher reliability and stability, while enriching the matrix of the VIPerPlus series product line.
After years of development, the VIPerPlus series products have also introduced gallium nitride technology, and a new generation of VIPerGaN production series products have been developed. Thanks to the efficient and high power density characteristics of gallium nitride technology, the power limit of the VIPerGaN production series products has been increased to 100W, obtaining a wider range of application space.
VIPerGaN is a highly integrated gallium nitride chip with advanced PWM controller and 650V GaN power transistor. It integrates high-voltage starting function, no-load loss less than 30mW, adaptive dynamic blanking time and adjustable valley bottom synchronization, adaptive burp mode, etc. It also has complete protection functions, with a switching frequency of up to 240kHz. It is a high-efficiency, high-power density chip that adopts the QFN5x6 packaging process to effectively optimize the layout space of the PCB board and reduce peripheral components, achieving better EMI performance. This solution not only meets energy efficiency requirements but also has lower BoM costs, making it very suitable for manufacturers in the fields of chargers and adapters, home appliances, air conditioning, consumer goods, and other fields.
The advantage of integrating GaN chips is that they achieve direct drive of gallium nitride within the chip. Through a sealing scheme, parasitic parameters caused by external wiring are further reduced, thereby reducing the impact of parasitic oscillations on high-frequency switches and minimizing the interference of gallium nitride. Compared to separate GaN solutions, they have more advantages.
The above is the pin distribution diagram of VIPerGaN. From the figure, it can be seen that VIPerGaN has very few pins, but its functional configuration is very rich and flexible. Different pins can achieve different functions and have complete protection functions.
The VIPer series products have higher reliability under uncertain input voltage settings based on input OVP/Brin out settings. The Brown in protection function is used to define the minimum input startup voltage. When the voltage is higher than the set voltage, the chip will emit PWM drive; Brown out is used to define when the input shutdown voltage is lower than the set voltage, and the chip will shut down the driver, thereby protecting the product; The input OVP protection function plays a role in protecting the converter when the input bus voltage is overvoltage. If the user does not need to use this function, simply short circuit to the ground.

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